1. Technical Field
The embodiments herein generally relate to LDPC decoder, and, more particularly, to a system and method for implementing multi standard programmable LDPC decoder.
2. Description of the Related Art
Low-density parity-check (LDPC) code are a class of linear block codes which provide near capacity performance on a large collection of data transmission over noisy channels while simultaneously admitting implementable decoders. An LDPC code is specified by defining a matrix called H-matrix that indicates how parity bits are calculated. An H-matrix is a sparse matrix, but it is possible in many cases (e.g., DVB-T2/S2/C2) to rearrange the rows so that it forms a more regular structure. The H-matrix is composed of smaller sub-matrices. LDPC H-matrices are different across the standards and also they are different for different code rates within the same standard such as DVB-T2/S2/C2, 802.11, 802.3, 802.16, and CDMB-T etc. Therefore, due to this variation in the H-Matrices, existing LDPC decoders are designed to decode only a particular standard, hence they can't be used to decode other LDPC codes. One of the ways of implementing an LDPC decoder is to specifically target to a particular standard. A method of implementing the LDPC decoder could be, control signals for further processing are generated using hardware logic (e.g., an H-matrix parser module) where by reading memory associated with the H-Matrix. This option is restricted by the structure of the H-Matrix and its attributes like block length, maximum row weight, size of the sub matrix and number of rows in a layer etc. The H-matrix attributes are decoded by hardwired logic to generate control signals for the rest of the processing pipeline. When the attributes of the H-Matrix vary, hardware block fails to handle those variations. Hence this cannot implement different H-Matrices of various standards. If any other standards to be implemented in this architecture, then there is a need to make changes in the existing hardware architecture. Accordingly, there remains a need for a system and a method to design better LDPC decoder which supports different standards and to avoid a memory access conflicts without making changes in the existing hardware architecture.